1. Field of the Invention
The present invention relates to an electrostatic discharge protection (ESD) circuit, and more particularly, to an ESD protection circuit applied to an IC with power-down-mode operation.
2. Description of the Prior Art
For power consumption consideration, an IC with power-down-mode operation becomes more and more attractive especially in the SOC (System on a Chip) design for the portable and mobile devices. FIG. 1 shows an example of two chips connected in a system 10, wherein a first chip 12 is biased by the VDD1 power line 14 and a second chip 16 is biased by the VDD2 power line 18. Besides, the output pad 20 of the first chip 12 is connected to the input pad 22 of the second chip 16. When the second chip 16 goes into the power-down-mode operation and the output voltage level of the first chip 12 is high, two situations are explained as follows. First, if VDD2 power line 18 is grounded, large leakage current may be induced from the output pad 20 to the VDD2 power line 18 through the input pad 22 and the parasitic diode 24 of PMOS that is connected between the input pad 22 and VDD2 power line 18. Second, if the VDD2 power line 18 is floating, the high level voltage of the output pad 20 will charge the VDD2 power line 18 through the input pad 22 and the parasitic diode 24 of PMOS, and then the internal circuit 26 of the second chip 16 may be triggered and results in malfunction. Therefore, the parasitic diode 24 of PMOS connected between the input pad and VDD2 power line need to be removed to avoid the problems described above.
To avoid unexpected ESD damage in the integrated circuits, the ESD design is needed for most ICs. FIG. 2 is a scheme showing the traditional ESD protection circuit. According to FIG. 2, when the ESD protection circuit is under the positive-to-VSS ESD mode, the VSS power line 34 is grounded. Then the positive electrostatic charge at the I/O pad 30, 32 can be discharged through the parasitic diode 36 of PMOS, the VDD power line 38 and the power-rail ESD clamp circuit 40 to the VSS power line 34. When the ESD protection circuit is under the positive-to-VDD ESD mode, the VDD power line 38 is grounded and the positive electrostatic charge at the I/O pad 30, 32 can be discharged through the parasitic diode 36 of PMOS to VDD power line 38. In addition, when the ESD protection circuits are under the negative-to-VSS ESD mode, the VSS power line 34 is grounded and then the negative electrostatic charge at the I/O pad 30, 32 can be discharged through the parasitic diode 42 of NMOS to VSS power line 34. Furthermore, when the ESD protection circuits are under the negative-to-VDD ESD mode, the VSS power line 34 is grounded and thus the negative electrostatic charge at the I/O pad 30, 32 can be discharged through the parasitic diode 42 of NMOS, VSS power line 34, and power-rail ESD clamp circuit 40 to the VDD power line 38.
According to the description in the first paragraph, the parasitic diode of PMOS must be removed under the power-down-mode operation. However, if the ESD protection circuit stated in the second paragraph applies to the IC with power-down-mode operation, the electrostatic charge at the I/O pad under positive-to-VSS mode can't be discharged through the parasitic of the PMOS, the VDD power line, and the power-rail ESD clamp circuit to VSS power line. Hence, the positive-to-VSS voltage on the I/O pad is discharged to the VSS power line merely by the snapback breakdown of the GGNMOS (Gate-Grounded NMOS). Due to the junction breakdown voltage is close to the oxide breakdown voltage as the device shrinks, the GGNMOS could not provide efficient ESD protection. At the same time, the non-uniform turn-on issue often lowers the ESD level of the GGNMOS and the positive-to-VDD ESD voltage zapping on the I/O pad cannot be discharged from the I/O pad to VDD power line without causing the PMOS breakdown. Therefore, such positive-to-VDD ESD voltage on the I/O pad will also be discharged through the GGNMOS by snapback breakdown to the VSS line, and then through the power-rail ESD clamp circuit to the grounded VDD power line. For the reasons stated above, the disappearance of the parasitic diode of PMOS may severely degrade the ESD performance.
In order to solve the above problems, someone replaces the parasitic diode of the PMOS with GGNMOS as disclosed in USA patent “ESD protection circuit and method for power-down application” (U.S. Pat. No. 5,229,635). However, the GGNMOS that discharges electrostatic charge with snapback breakdown will turn on irregularly and result in a poor ESD protection effect. Besides, someone teaches the design for improving the ESD robustness of the ESD protection circuit connected between the I/O pad and VSS power line as reported in “Tech. Dig. Of IEDM, 2002, pp. 349–352”. According to this design, all electrostatic charge discharges via the ESD protection circuit connected between the I/O pad and the VSS power line. However, this ESD protection circuit is too complicated and the consumption for ESD protection is much higher.